| ammonite-git |
r2276.2aa3f84e-1 |
0 |
0.00 |
Scala Scripting |
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| bluespec-git |
r301.9f4a447-107 |
2 |
0.04 |
Bluespec Compiler (BSC) |
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| diagrammer-git |
r81.18bae5b-1 |
1 |
0.19 |
Provides dot visualizations of chisel/firrtl circuites |
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| dromajo |
1.0-1 |
0 |
0.00 |
|
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| dromajo-git |
1.0.r25.gee470be-1 |
0 |
0.00 |
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| eda-meta |
1-1 |
0 |
0.00 |
meta package to define a basic EDA(chisel Cadence Synopsys Mentor) Server installation |
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| gitmirror |
1.0.0-1 |
0 |
0.00 |
Auto sync GitHub to GitLab |
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| mill-git |
r1367.fb6fee27-1 |
1 |
0.04 |
Your shiny new Java/Scala build tool |
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| openroad-git |
r1370.c60f9724-1 |
0 |
0.00 |
A framework for RTL synthesis |
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| opensta-git |
r156.73fef11-1 |
0 |
0.00 |
A gate level static timing verifier. |
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| plume |
0.3.0a2-1 |
0 |
0.00 |
Federated blogging application |
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| python-gdspy-git |
r461.d440538-1 |
0 |
0.00 |
Python module for creating GDSII stream files, usually CAD layouts. |
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| riscv-openocd-git |
v20180629.r1233.gc116dc50b-1 |
0 |
0.00 |
Fork of OpenOCD that has RISC-V support |
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| riscv-pk-git |
1-1 |
0 |
0.00 |
RISC-V proxy kernel and boot loader |
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| riscv-sifive-elf-binutils |
2.32-1 |
0 |
0.00 |
A set of programs to assemble and manipulate binary and object files for the RISC-V (bare-metal) target |
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| riscv-sifive-elf-gcc |
9.1.0-1 |
0 |
0.00 |
Cross compiler for 32-bit and 64-bit RISC-V |
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| riscv-sifive-elf-gcc-stage1 |
9.1.0-1 |
0 |
0.00 |
Cross compiler for 32-bit and 64-bit RISC-V |
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| riscv-sifive-elf-gdb |
8.3-1 |
0 |
0.00 |
The GNU Debugger for the RISC-V (bare-metal) target |
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| riscv-sifive-elf-newlib |
3.1.0-1 |
0 |
0.00 |
A C standard library implementation intended for use on embedded systems (RISC-V bare metal) |
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| riscv-tests-git |
1-1 |
0 |
0.00 |
Hosts unit tests for RISC-V processors. |
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| spike-git |
1-1 |
0 |
0.00 |
Spike, a RISC-V ISA Simulator |
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| svd2rust |
0.17.0-1 |
0 |
0.00 |
Generate Rust register maps (`struct`s) from SVD files |
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| wake-git |
r1216.f64b193-1 |
0 |
0.00 |
The SiFive wake build tool |
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| xilinx-hw-server |
2019.2-1 |
0 |
0.00 |
A software suite produced by Xilinx for synthesis and analysis of HDL designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis. |
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| xswitcher-git |
r6.4bd85fc-1 |
1 |
0.29 |
quick script to fiddle with xorg.conf when using an eGPU |
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