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authorxantares2015-06-08 23:12:23 +0200
committerxantares2015-06-08 23:12:23 +0200
commit8b3302621209448bb6ec9d1355bf2339229e4f7b (patch)
treefb657d9fd97c5d3a22014f224a11c75190fa8885
downloadaur-8b3302621209448bb6ec9d1355bf2339229e4f7b.tar.gz
Initial import
-rw-r--r--.SRCINFO33
-rw-r--r--PKGBUILD52
-rw-r--r--gcc-4.6.4-PSP.patch843
3 files changed, 928 insertions, 0 deletions
diff --git a/.SRCINFO b/.SRCINFO
new file mode 100644
index 00000000000..cc553d6093e
--- /dev/null
+++ b/.SRCINFO
@@ -0,0 +1,33 @@
+pkgbase = psp-gcc
+ pkgdesc = The GNU Compiler Collection - C and C++ frontends (psp)
+ pkgver = 4.6.4
+ pkgrel = 1
+ url = http://gcc.gnu.org
+ arch = i686
+ arch = x86_64
+ groups = psp
+ license = GPL
+ license = LGPL
+ license = FDL
+ license = custom
+ depends = psp-binutils
+ depends = psp-newlib
+ depends = mpfr
+ provides = psp-gcc-base
+ conflicts = psp-gcc-base
+ options = !buildflags
+ options = !strip
+ options = staticlibs
+ source = http://ftp.gnu.org/pub/gnu/gcc/gcc-4.6.4/gcc-4.6.4.tar.bz2
+ source = gcc-4.6.4-PSP.patch
+ source = ftp://ftp.gmplib.org/pub/gmp-5.1.3/gmp-5.1.3.tar.bz2
+ source = http://www.multiprecision.org/mpc/download/mpc-1.0.2.tar.gz
+ source = http://www.mpfr.org/mpfr-3.1.2/mpfr-3.1.2.tar.bz2
+ md5sums = b407a3d1480c11667f293bfb1f17d1a4
+ md5sums = fde0c20f56e608715ec13d5d8b8c8e59
+ md5sums = a082867cbca5e898371a97bb27b31fea
+ md5sums = 68fadff3358fb3e7976c7a398a0af4c3
+ md5sums = ee2c3ac63bf0c2359bf08fc3ee094c19
+
+pkgname = psp-gcc
+
diff --git a/PKGBUILD b/PKGBUILD
new file mode 100644
index 00000000000..cd21fcb1a07
--- /dev/null
+++ b/PKGBUILD
@@ -0,0 +1,52 @@
+# Maintainer: xantares <xantares09 at hotmail dot com>
+
+pkgname=psp-gcc
+pkgver=4.6.4
+pkgrel=1
+pkgdesc="The GNU Compiler Collection - C and C++ frontends (psp)"
+arch=(i686 x86_64)
+url="http://gcc.gnu.org"
+license=('GPL' 'LGPL' 'FDL' 'custom')
+groups=('psp')
+depends=('psp-binutils' 'psp-newlib' 'mpfr')
+conflicts=('psp-gcc-base')
+provides=('psp-gcc-base')
+options=('!buildflags' '!strip' 'staticlibs')
+source=("http://ftp.gnu.org/pub/gnu/gcc/gcc-$pkgver/gcc-$pkgver.tar.bz2"
+ "gcc-$pkgver-PSP.patch"
+ "ftp://ftp.gmplib.org/pub/gmp-5.1.3/gmp-5.1.3.tar.bz2"
+ "http://www.multiprecision.org/mpc/download/mpc-1.0.2.tar.gz"
+ "http://www.mpfr.org/mpfr-3.1.2/mpfr-3.1.2.tar.bz2")
+md5sums=('b407a3d1480c11667f293bfb1f17d1a4'
+ 'fde0c20f56e608715ec13d5d8b8c8e59'
+ 'a082867cbca5e898371a97bb27b31fea'
+ '68fadff3358fb3e7976c7a398a0af4c3'
+ 'ee2c3ac63bf0c2359bf08fc3ee094c19')
+
+prepare ()
+{
+ cd "$srcdir/gcc-$pkgver"
+ rm -f gcc/config/mips/allegrex.md gcc/config/mips/psp.h gcc/config/mips/t-allegrex
+ patch -p1 -i "$srcdir"/gcc-$pkgver-PSP.patch
+ ln -sf "$srcdir"/gmp-5.1.3 gmp
+ ln -sf "$srcdir"/mpc-1.0.2 mpc
+ ln -sf "$srcdir"/mpfr-3.1.2 mpfr
+}
+
+build()
+{
+ cd "$srcdir/gcc-$pkgver"
+ mkdir -p build-psp && pushd build-psp
+ ../configure --prefix=/usr --target=psp \
+ --enable-languages="c,c++" --enable-lto --with-newlib --with-gmp --with-mpfr --enable-cxx-flags="-G0"
+ make
+}
+
+package()
+{
+ cd "$srcdir/gcc-$pkgver/build-psp"
+ make install DESTDIR="$pkgdir"
+ rm -r "$pkgdir"/usr/share
+ rm "$pkgdir"/usr/lib/libiberty.a
+}
+
diff --git a/gcc-4.6.4-PSP.patch b/gcc-4.6.4-PSP.patch
new file mode 100644
index 00000000000..d71595a5ebc
--- /dev/null
+++ b/gcc-4.6.4-PSP.patch
@@ -0,0 +1,843 @@
+diff -Nbaur gcc-4.6.4/config.sub gcc-4.6.4-psp/config.sub
+--- gcc-4.6.4/config.sub 2010-05-25 09:22:07.000000000 -0400
++++ gcc-4.6.4-psp/config.sub 2014-06-09 18:54:13.013936018 -0400
+@@ -279,6 +279,7 @@
+ | mipsisa64sb1 | mipsisa64sb1el \
+ | mipsisa64sr71k | mipsisa64sr71kel \
+ | mipstx39 | mipstx39el \
++ | mipsallegrex | mipsallegrexel \
+ | mn10200 | mn10300 \
+ | moxie \
+ | mt \
+@@ -375,6 +376,7 @@
+ | mipsisa64sb1-* | mipsisa64sb1el-* \
+ | mipsisa64sr71k-* | mipsisa64sr71kel-* \
+ | mipstx39-* | mipstx39el-* \
++ | mipsallegrex-* | mipsallegrexel-* \
+ | mmix-* \
+ | mt-* \
+ | msp430-* \
+@@ -771,6 +773,10 @@
+ basic_machine=m68k-atari
+ os=-mint
+ ;;
++ psp)
++ basic_machine=mipsallegrexel-psp
++ os=-elf
++ ;;
+ mips3*-*)
+ basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
+ ;;
+diff -Nbaur gcc-4.6.4/gcc/config/mips/allegrex.md gcc-4.6.4-psp/gcc/config/mips/allegrex.md
+--- gcc-4.6.4/gcc/config/mips/allegrex.md 1969-12-31 19:00:00.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/allegrex.md 2014-06-09 18:54:13.013936018 -0400
+@@ -0,0 +1,191 @@
++;; Sony ALLEGREX instructions.
++;; Copyright (C) 2005 Free Software Foundation, Inc.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify
++;; it under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 2, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful,
++;; but WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++;; GNU General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING. If not, write to
++;; the Free Software Foundation, 59 Temple Place - Suite 330,
++;; Boston, MA 02111-1307, USA.
++
++(define_c_enum "unspec" [
++ UNSPEC_WSBH
++ UNSPEC_CLO
++ UNSPEC_CTO
++ UNSPEC_CACHE
++ UNSPEC_CEIL_W_S
++ UNSPEC_FLOOR_W_S
++ UNSPEC_ROUND_W_S
++])
++
++;; Multiply Add and Subtract.
++;; Note: removed clobbering for madd and msub (testing needed)
++
++(define_insn "allegrex_madd"
++ [(set (match_operand:SI 0 "register_operand" "+l")
++ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "register_operand" "d"))
++ (match_dup 0)))]
++ "TARGET_ALLEGREX"
++ "madd\t%1,%2"
++ [(set_attr "type" "imadd")
++ (set_attr "mode" "SI")])
++
++(define_insn "allegrex_msub"
++ [(set (match_operand:SI 0 "register_operand" "+l")
++ (minus:SI (match_dup 0)
++ (mult:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "register_operand" "d"))))]
++ "TARGET_ALLEGREX"
++ "msub\t%1,%2"
++ [(set_attr "type" "imadd")
++ (set_attr "mode" "SI")])
++
++
++;; Min and max.
++
++(define_insn "sminsi3"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (smin:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "register_operand" "d")))]
++ "TARGET_ALLEGREX"
++ "min\t%0,%1,%2"
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")])
++
++(define_insn "smaxsi3"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (smax:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "register_operand" "d")))]
++ "TARGET_ALLEGREX"
++ "max\t%0,%1,%2"
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")])
++
++
++;; Extended shift instructions.
++
++(define_insn "allegrex_bitrev"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
++ UNSPEC_BITREV))]
++ "TARGET_ALLEGREX"
++ "bitrev\t%0,%1"
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")])
++
++(define_insn "allegrex_wsbh"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
++ UNSPEC_WSBH))]
++ "TARGET_ALLEGREX"
++ "wsbh\t%0,%1"
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")])
++
++(define_insn "bswapsi2"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
++ "TARGET_ALLEGREX"
++ "wsbw\t%0,%1"
++ [(set_attr "type" "shift")
++ (set_attr "mode" "SI")])
++
++
++;; Count leading ones, count trailing zeros, and count trailing ones (clz is
++;; already defined).
++
++(define_insn "allegrex_clo"
++ [(set (match_operand:SI 0 "register_operand" "=d")
++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
++ UNSPEC_CLO))]
++ "TARGET_ALLEGREX"
++ "clo\t%0,%1"
++ [(set_attr "type" "clz")
++ (set_attr "mode" "SI")])
++
++(define_expand "ctzsi2"
++ [(set (match_operand:SI 0 "register_operand")
++ (ctz:SI (match_operand:SI 1 "register_operand")))]
++ "TARGET_ALLEGREX"
++{
++ rtx r1;
++
++ r1 = gen_reg_rtx (SImode);
++ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
++ emit_insn (gen_clzsi2 (operands[0], r1));
++ DONE;
++})
++
++(define_expand "allegrex_cto"
++ [(set (match_operand:SI 0 "register_operand")
++ (unspec:SI [(match_operand:SI 1 "register_operand")]
++ UNSPEC_CTO))]
++ "TARGET_ALLEGREX"
++{
++ rtx r1;
++
++ r1 = gen_reg_rtx (SImode);
++ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
++ emit_insn (gen_allegrex_clo (operands[0], r1));
++ DONE;
++})
++
++
++;; Misc.
++
++(define_insn "allegrex_sync"
++ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
++ "TARGET_ALLEGREX"
++ "sync"
++ [(set_attr "type" "unknown")
++ (set_attr "mode" "none")])
++
++(define_insn "allegrex_cache"
++ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
++ (match_operand:SI 1 "register_operand" "d")]
++ UNSPEC_CACHE)]
++ "TARGET_ALLEGREX"
++ "cache\t%0,0(%1)"
++ [(set_attr "type" "unknown")
++ (set_attr "mode" "none")])
++
++
++;; Floating-point builtins.
++
++(define_insn "allegrex_ceil_w_s"
++ [(set (match_operand:SI 0 "register_operand" "=f")
++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
++ UNSPEC_CEIL_W_S))]
++ "TARGET_ALLEGREX"
++ "ceil.w.s\t%0,%1"
++ [(set_attr "type" "fcvt")
++ (set_attr "mode" "SF")])
++
++(define_insn "allegrex_floor_w_s"
++ [(set (match_operand:SI 0 "register_operand" "=f")
++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
++ UNSPEC_FLOOR_W_S))]
++ "TARGET_ALLEGREX"
++ "floor.w.s\t%0,%1"
++ [(set_attr "type" "fcvt")
++ (set_attr "mode" "SF")])
++
++(define_insn "allegrex_round_w_s"
++ [(set (match_operand:SI 0 "register_operand" "=f")
++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
++ UNSPEC_ROUND_W_S))]
++ "TARGET_ALLEGREX"
++ "round.w.s\t%0,%1"
++ [(set_attr "type" "fcvt")
++ (set_attr "mode" "SF")])
+diff -Nbaur gcc-4.6.4/gcc/config/mips/mips.c gcc-4.6.4-psp/gcc/config/mips/mips.c
+--- gcc-4.6.4/gcc/config/mips/mips.c 2012-09-02 06:37:49.000000000 -0400
++++ gcc-4.6.4-psp/gcc/config/mips/mips.c 2014-06-09 18:54:13.021936018 -0400
+@@ -239,7 +239,12 @@
+ MIPS_BUILTIN_CMP_SINGLE,
+
+ /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
+- MIPS_BUILTIN_BPOSGE32
++ MIPS_BUILTIN_BPOSGE32,
++
++ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
++ is the function code (must be less than 32) and operand 1 is the base
++ address. */
++ MIPS_BUILTIN_CACHE
+ };
+
+ /* Invoke MACRO (COND) for each C.cond.fmt condition. */
+@@ -516,6 +521,10 @@
+ normal branch. */
+ static bool mips_branch_likely;
+
++/* Preferred stack boundary for proper stack vars alignment */
++unsigned int mips_preferred_stack_boundary;
++unsigned int mips_preferred_stack_align;
++
+ /* The current instruction-set architecture. */
+ enum processor mips_arch;
+ const struct mips_cpu_info *mips_arch_info;
+@@ -691,6 +700,7 @@
+
+ /* MIPS II processors. */
+ { "r6000", PROCESSOR_R6000, 2, 0 },
++ { "allegrex", PROCESSOR_ALLEGREX, 2, 0 },
+
+ /* MIPS III processors. */
+ { "r4000", PROCESSOR_R4000, 3, 0 },
+@@ -969,6 +979,9 @@
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
++ { /* Allegrex */
++ DEFAULT_COSTS
++ },
+ { /* Loongson-2E */
+ DEFAULT_COSTS
+ },
+@@ -12605,6 +12618,7 @@
+ AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
+ AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
+ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
++AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
+
+ /* Construct a mips_builtin_description from the given arguments.
+
+@@ -12701,6 +12715,30 @@
+ MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
+ MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
+
++/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
++ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
++#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
++
++/* Same as the above, but mapped to an instruction that doesn't share the
++ NAME. NAME is the name of the builtin without the builtin prefix. */
++#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
++ { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
++
++/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
++ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
++ builtin_description fields. */
++#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
++ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
++
++/* Define a builtin with a specific function TYPE. */
++#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
++ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
++
+ /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
+ for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
+ builtin_description field. */
+@@ -12945,6 +12983,40 @@
+ DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
+ DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
+
++/* Builtin functions for the Sony ALLEGREX processor.
++
++ These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
++ to maintain compatibility with Sony's ALLEGREX GCC port.
++
++ Some of the builtins may seem redundant, but they are the same as the
++ builtins defined in the Sony compiler. I chose to map redundant and
++ trivial builtins to the original instruction instead of creating
++ duplicate patterns specifically for the ALLEGREX (as Sony does). */
++
++ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
++
++ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
++
++ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
++ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
++
++ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
++ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
++ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
++ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
++ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
++
+ /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
+ LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
+ LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
+@@ -13096,6 +13168,8 @@
+ /* Standard mode-based argument types. */
+ #define MIPS_ATYPE_UQI unsigned_intQI_type_node
+ #define MIPS_ATYPE_SI intSI_type_node
++#define MIPS_ATYPE_HI intHI_type_node
++#define MIPS_ATYPE_QI intQI_type_node
+ #define MIPS_ATYPE_USI unsigned_intSI_type_node
+ #define MIPS_ATYPE_DI intDI_type_node
+ #define MIPS_ATYPE_UDI unsigned_intDI_type_node
+@@ -13270,6 +13344,9 @@
+
+ switch (opno)
+ {
++ case 0:
++ emit_insn (GEN_FCN (icode) (0));
++ break;
+ case 2:
+ emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
+ break;
+@@ -13439,6 +13516,28 @@
+ const1_rtx, const0_rtx);
+ }
+
++/* Expand a __builtin_allegrex_cache() function. Make sure the passed
++ cache function code is less than 32. */
++
++static rtx
++mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
++{
++ rtx op0, op1;
++
++ op0 = mips_prepare_builtin_arg (icode, 0, exp, 0);
++ op1 = mips_prepare_builtin_arg (icode, 1, exp, 1);
++
++ if (GET_CODE (op0) == CONST_INT)
++ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
++ {
++ error ("invalid function code '%d'", INTVAL (op0));
++ return const0_rtx;
++ }
++
++ emit_insn (GEN_FCN (icode) (op0, op1));
++ return target;
++}
++
+ /* Implement TARGET_EXPAND_BUILTIN. */
+
+ static rtx
+@@ -13484,6 +13583,9 @@
+
+ case MIPS_BUILTIN_BPOSGE32:
+ return mips_expand_builtin_bposge (d->builtin_type, target);
++
++ case MIPS_BUILTIN_CACHE:
++ return mips_expand_builtin_cache (d->icode, target, exp);
+ }
+ gcc_unreachable ();
+ }
+@@ -15921,6 +16023,22 @@
+ Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
+ MIPS16 mode afterwards if need be. */
+ mips_set_mips16_mode (false);
++
++ /* Validate -mpreferred-stack-boundary= value, or provide default.
++ The default of 128-bit is for newABI else 64-bit. */
++ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
++ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
++ if (mips_preferred_stack_boundary_string)
++ {
++ i = atoi (mips_preferred_stack_boundary_string);
++ if (i < 2 || i > 12)
++ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
++ else
++ {
++ mips_preferred_stack_align = (1 << i);
++ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
++ }
++ }
+ }
+
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+diff -Nbaur gcc-4.6.4/gcc/config/mips/mips-ftypes.def gcc-4.6.4-psp/gcc/config/mips/mips-ftypes.def
+--- gcc-4.6.4/gcc/config/mips/mips-ftypes.def 2009-02-20 10:20:38.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/mips-ftypes.def 2014-06-09 18:54:13.013936018 -0400
+@@ -53,9 +53,12 @@
+
+ DEF_MIPS_FTYPE (2, (SI, DI, SI))
+ DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
++DEF_MIPS_FTYPE (1, (SI, HI))
++DEF_MIPS_FTYPE (1, (SI, SF))
+ DEF_MIPS_FTYPE (1, (SI, SI))
+ DEF_MIPS_FTYPE (2, (SI, SI, SI))
+ DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
++DEF_MIPS_FTYPE (1, (SI, QI))
+ DEF_MIPS_FTYPE (1, (SI, V2HI))
+ DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
+ DEF_MIPS_FTYPE (1, (SI, V4QI))
+@@ -124,3 +127,4 @@
+ DEF_MIPS_FTYPE (2, (VOID, SI, SI))
+ DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
+ DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
++DEF_MIPS_FTYPE (1, (VOID, VOID))
+diff -Nbaur gcc-4.6.4/gcc/config/mips/mips.h gcc-4.6.4-psp/gcc/config/mips/mips.h
+--- gcc-4.6.4/gcc/config/mips/mips.h 2011-03-08 15:51:11.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/mips.h 2014-06-09 18:54:13.021936018 -0400
+@@ -231,6 +231,7 @@
+ #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
+ || mips_arch == PROCESSOR_SB1A)
+ #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
++#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
+
+ /* Scheduling target defines. */
+ #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
+@@ -258,6 +259,7 @@
+ #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
+ #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
+ || mips_tune == PROCESSOR_SB1A)
++#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
+
+ /* Whether vector modes and intrinsics for ST Microelectronics
+ Loongson-2E/2F processors should be enabled. In o32 pairs of
+@@ -852,6 +854,9 @@
+ /* ISA has LDC1 and SDC1. */
+ #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+
++/* ISA has just the integer condition move instructions (movn,movz) */
++#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
++
+ /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
+ branch on CC, and move (both FP and non-FP) on CC. */
+ #define ISA_HAS_8CC (ISA_MIPS4 \
+@@ -874,6 +879,7 @@
+
+ /* ISA has conditional trap instructions. */
+ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
++ && !TARGET_ALLEGREX \
+ && !TARGET_MIPS16)
+
+ /* ISA has integer multiply-accumulate instructions, madd and msub. */
+@@ -910,6 +916,7 @@
+ /* ISA has count leading zeroes/ones instruction (not implemented). */
+ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
+ || ISA_MIPS32R2 \
++ || TARGET_ALLEGREX \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
+ && !TARGET_MIPS16)
+@@ -955,6 +962,7 @@
+ || TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
++ || TARGET_ALLEGREX \
+ || TARGET_SMARTMIPS) \
+ && !TARGET_MIPS16)
+
+@@ -984,11 +992,13 @@
+
+ /* ISA includes the MIPS32r2 seb and seh instructions. */
+ #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
++ || TARGET_ALLEGREX \
+ || ISA_MIPS64R2) \
+ && !TARGET_MIPS16)
+
+ /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
+ #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
++ || TARGET_ALLEGREX \
+ || ISA_MIPS64R2) \
+ && !TARGET_MIPS16)
+
+@@ -1038,7 +1048,8 @@
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2 \
+ || TARGET_MIPS5500 \
+- || TARGET_LOONGSON_2EF)
++ || TARGET_LOONGSON_2EF \
++ || TARGET_ALLEGREX)
+
+ /* ISA includes synci, jr.hb and jalr.hb. */
+ #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
+@@ -2133,7 +2144,7 @@
+ `crtl->outgoing_args_size'. */
+ #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
+
+-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
++#define STACK_BOUNDARY (mips_preferred_stack_boundary)
+
+ /* Symbolic macros for the registers used to return integer and floating
+ point values. */
+@@ -2259,7 +2270,7 @@
+ /* Treat LOC as a byte offset from the stack pointer and round it up
+ to the next fully-aligned offset. */
+ #define MIPS_STACK_ALIGN(LOC) \
+- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
++ (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
+
+
+ /* Output assembler code to FILE to increment profiler label # LABELNO
+@@ -2911,6 +2922,9 @@
+ #endif
+ #endif
+
++extern unsigned int mips_preferred_stack_boundary;
++extern unsigned int mips_preferred_stack_align;
++
+ #ifndef HAVE_AS_TLS
+ #define HAVE_AS_TLS 0
+ #endif
+diff -Nbaur gcc-4.6.4/gcc/config/mips/mips.md gcc-4.6.4-psp/gcc/config/mips/mips.md
+--- gcc-4.6.4/gcc/config/mips/mips.md 2012-01-09 17:09:53.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/mips.md 2014-06-09 18:54:13.021936018 -0400
+@@ -37,6 +37,7 @@
+ 74kf2_1
+ 74kf1_1
+ 74kf3_2
++ allegrex
+ loongson_2e
+ loongson_2f
+ loongson_3a
+@@ -598,7 +599,7 @@
+ ;; This mode iterator allows :MOVECC to be used anywhere that a
+ ;; conditional-move-type condition is needed.
+ (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
+- (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
++ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")])
+
+ ;; 32-bit integer moves for which we provide move patterns.
+ (define_mode_iterator IMOVE32
+@@ -1885,11 +1886,11 @@
+ (mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
+- "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
++ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
+ {
+ if (ISA_HAS_DSP_MULT)
+ return "msub<u>\t%q0,%1,%2";
+- else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
++ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
+ return "msub<u>\t%1,%2";
+ else
+ return "msac<u>\t$0,%1,%2";
+@@ -2066,14 +2067,14 @@
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
+ (match_operand:DI 3 "register_operand" "0")))]
+- "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
++ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
+ && !TARGET_64BIT"
+ {
+ if (TARGET_MAD)
+ return "mad<u>\t%1,%2";
+ else if (ISA_HAS_DSP_MULT)
+ return "madd<u>\t%q0,%1,%2";
+- else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
++ else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
+ return "madd<u>\t%1,%2";
+ else
+ /* See comment in *macc. */
+@@ -2500,6 +2501,33 @@
+ ;;
+ ;; ....................
+ ;;
++;; FIND FIRST BIT INSTRUCTION
++;;
++;; ....................
++;;
++
++(define_expand "ffs<mode>2"
++ [(set (match_operand:GPR 0 "register_operand" "")
++ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
++ "ISA_HAS_CLZ_CLO"
++{
++ rtx r1, r2, r3, r4;
++
++ r1 = gen_reg_rtx (<MODE>mode);
++ r2 = gen_reg_rtx (<MODE>mode);
++ r3 = gen_reg_rtx (<MODE>mode);
++ r4 = gen_reg_rtx (<MODE>mode);
++ emit_insn (gen_neg<mode>2 (r1, operands[1]));
++ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
++ emit_insn (gen_clz<mode>2 (r3, r2));
++ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
++ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
++ DONE;
++})
++
++;;
++;; ....................
++;;
+ ;; NEGATION and ONE'S COMPLEMENT
+ ;;
+ ;; ....................
+@@ -2550,6 +2578,25 @@
+ [(set_attr "alu_type" "not")
+ (set_attr "mode" "<MODE>")])
+
++(define_expand "rotl<mode>3"
++ [(set (match_operand:GPR 0 "register_operand")
++ (rotate:GPR (match_operand:GPR 1 "register_operand")
++ (match_operand:SI 2 "arith_operand")))]
++ "ISA_HAS_ROR"
++{
++ rtx temp;
++
++ if (GET_CODE (operands[2]) == CONST_INT)
++ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
++ else
++ {
++ temp = gen_reg_rtx (<MODE>mode);
++ emit_insn (gen_neg<mode>2 (temp, operands[2]));
++ }
++ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
++ DONE;
++})
++
+ ;;
+ ;; ....................
+ ;;
+@@ -6301,7 +6348,7 @@
+ (const_int 0)])
+ (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
+- "ISA_HAS_CONDMOVE"
++ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "@
+ mov%T4\t%0,%z2,%1
+ mov%t4\t%0,%z3,%1"
+@@ -6331,8 +6378,12 @@
+ (if_then_else:GPR (match_dup 5)
+ (match_operand:GPR 2 "reg_or_0_operand")
+ (match_operand:GPR 3 "reg_or_0_operand")))]
+- "ISA_HAS_CONDMOVE"
++ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ {
++ if (ISA_HAS_INT_CONDMOVE
++ && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
++ FAIL;
++
+ mips_expand_conditional_move (operands);
+ DONE;
+ })
+@@ -6481,6 +6532,9 @@
+ ; ST-Microelectronics Loongson-2E/2F-specific patterns.
+ (include "loongson.md")
+
++; Sony ALLEGREX instructions.
++(include "allegrex.md")
++
+ (define_c_enum "unspec" [
+ UNSPEC_ADDRESS_FIRST
+ ])
+diff -Nbaur gcc-4.6.4/gcc/config/mips/mips.opt gcc-4.6.4-psp/gcc/config/mips/mips.opt
+--- gcc-4.6.4/gcc/config/mips/mips.opt 2011-02-16 20:59:04.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/mips.opt 2014-06-09 18:54:13.025936018 -0400
+@@ -306,5 +306,9 @@
+ Target Report Var(TARGET_XGOT)
+ Lift restrictions on GOT size
+
++mpreferred-stack-boundary=
++Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
++Attempt to keep stack aligned to this power of 2
++
+ noasmopt
+ Driver
+diff -Nbaur gcc-4.6.4/gcc/config/mips/psp.h gcc-4.6.4-psp/gcc/config/mips/psp.h
+--- gcc-4.6.4/gcc/config/mips/psp.h 1969-12-31 19:00:00.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/psp.h 2014-06-09 18:54:13.025936018 -0400
+@@ -0,0 +1,31 @@
++/* Support for Sony's Playstation Portable (PSP).
++ Copyright (C) 2005 Free Software Foundation, Inc.
++ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 2, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING. If not, write to
++the Free Software Foundation, 59 Temple Place - Suite 330,
++Boston, MA 02111-1307, USA. */
++
++/* Override the startfile spec to include crt0.o. */
++#undef STARTFILE_SPEC
++#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
++
++#undef SUBTARGET_CPP_SPEC
++#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
++
++/* Get rid of the .pdr section. */
++#undef SUBTARGET_ASM_SPEC
++#define SUBTARGET_ASM_SPEC "-mno-pdr"
+diff -Nbaur gcc-4.6.4/gcc/config/mips/t-allegrex gcc-4.6.4-psp/gcc/config/mips/t-allegrex
+--- gcc-4.6.4/gcc/config/mips/t-allegrex 1969-12-31 19:00:00.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config/mips/t-allegrex 2014-06-09 18:54:13.025936018 -0400
+@@ -0,0 +1,29 @@
++# Suppress building libgcc1.a, since the MIPS compiler port is complete
++# and does not need anything from libgcc1.a.
++LIBGCC1 =
++CROSS_LIBGCC1 =
++
++EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
++# Don't let CTOR_LIST end up in sdata section.
++CRTSTUFF_T_CFLAGS = -G 0
++
++# Assemble startup files.
++$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
++ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
++ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
++
++$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
++ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
++ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
++
++# We must build libgcc2.a with -G 0, in case the user wants to link
++# without the $gp register.
++TARGET_LIBGCC2_CFLAGS = -G 0
++
++# Build the libraries for both hard and soft floating point
++
++MULTILIB_OPTIONS =
++MULTILIB_DIRNAMES =
++
++LIBGCC = stmp-multilib
++INSTALL_LIBGCC = install-multilib
+diff -Nbaur gcc-4.6.4/gcc/config.gcc gcc-4.6.4-psp/gcc/config.gcc
+--- gcc-4.6.4/gcc/config.gcc 2013-03-06 12:40:07.000000000 -0500
++++ gcc-4.6.4-psp/gcc/config.gcc 2014-06-09 18:54:13.025936018 -0400
+@@ -2037,6 +2037,18 @@
+ tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
+ tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
+ ;;
++mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
++ tm_file="elfos.h ${tm_file} mips/elf.h"
++ tmake_file=mips/t-allegrex
++ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
++ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
++ case ${target} in
++ mipsallegrex*-psp-elf*)
++ tm_file="${tm_file} mips/psp.h"
++ ;;
++ esac
++ use_fixproto=yes
++ ;;
+ mmix-knuth-mmixware)
+ tm_file="${tm_file} newlib-stdint.h"
+ need_64bit_hwint=yes
+diff -Nbaur gcc-4.6.4/gcc/crtstuff.c gcc-4.6.4-psp/gcc/crtstuff.c
+--- gcc-4.6.4/gcc/crtstuff.c 2010-12-23 07:08:21.000000000 -0500
++++ gcc-4.6.4-psp/gcc/crtstuff.c 2014-06-09 18:54:13.025936018 -0400
+@@ -48,7 +48,7 @@
+
+ /* Target machine header files require this define. */
+ #define IN_LIBGCC2
+-
++#define USED_FOR_TARGET
+ /* FIXME: Including auto-host is incorrect, but until we have
+ identified the set of defines that need to go into auto-target.h,
+ this will have to do. */
+diff -Nbaur gcc-4.6.4/libcpp/Makefile.in gcc-4.6.4-psp/libcpp/Makefile.in
+--- gcc-4.6.4/libcpp/Makefile.in 2013-04-12 05:58:00.000000000 -0400
++++ gcc-4.6.4-psp/libcpp/Makefile.in 2014-06-09 18:54:13.025936018 -0400
+@@ -212,8 +212,8 @@
+ # Note that we put the dependencies into a .Tpo file, then move them
+ # into place if the compile succeeds. We need this because gcc does
+ # not atomically write the dependency output file.
+-COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
+-POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
++COMPILE = $(COMPILE.base) -o $@
++POSTCOMPILE =
+ else
+ COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
+ $(depcomp) $(COMPILE.base)
+diff -Nbaur gcc-4.6.4/libgcc/config.host gcc-4.6.4-psp/libgcc/config.host
+--- gcc-4.6.4/libgcc/config.host 2011-11-23 17:15:54.000000000 -0500
++++ gcc-4.6.4-psp/libgcc/config.host 2014-06-09 18:54:13.025936018 -0400
+@@ -436,6 +436,8 @@
+ ;;
+ mipstx39-*-elf* | mipstx39el-*-elf*)
+ ;;
++mips*-psp-elf*)
++ ;;
+ mmix-knuth-mmixware)
+ extra_parts="crti.o crtn.o crtbegin.o crtend.o"
+ tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"